Abstract:

A partly parallel decoding structure for quasi-cyclic low density party check code (QC-LDPC) is presented. In this method, the original check matrix is split into several smaller ones, thus the check node update unit (CNU) is decomposed into multiple parallel units, which brings in great hardware resource reduction. By organizing the sequence of check node updating process and variable node updating process, they can be carried out at a same time of different small matrixes, thus the decoding rate of the decoder is improved. This method may be applied not only to irregular LDPC code, but also to the regular one. The implementation result indicates that comparing with the log-BP decode method in common use, the presented method can reduce the logic core sizes of the CNU and variable node update unit (VNU) by approximately 1/3 under the same bit-rate or can improve bit-rate by approximately 1/3 under the same logic core size. Furthermore, this method makes the CNU more symmetric with the VNU, so that the design can gain higher timing performance by inserting fewer stages of pipelines.

Key words: communication , transmission , technology,  , hardware , resources,  , matrix , split,  , quasi-cyclic , low , density , parity , check , code,  , BP , decoding,  , hardware , structure,  , FPGA