基于CPCIe高速总线的机载多核计算处理平台

doi:10.7527/S1000-6893.2021.25238

Abstract

Abstract: As the avionics system of small and medium aircraft has strict restrictions on the volume, power consumption and weight of the computing and processing platform, it is necessary to design the computing and processing platform with high performance, miniaturization and low power consumption. An airborne computing and processing platform architecture based on the CPCIe (CompactPCI Express) high-speed bus and multi-core processor is studied. The adaptability of multi-core processing and high-speed signal integrity to the avionics system is realized. A distributed airborne multi-core computing platform is designed and implemented based on the CPCIe high-speed bus. Signal integrity of the CPCIe bus is simulated and tested. The computing processing platform is implemented and verified in the avionics system. Compared with the traditional joint architecture and integrated modular architecture, the performance per watt of the platform proposed is improved to about 7 times and 5 times, the performance per cubic centimeter is improved to about 24 times and 2 times, and the performance per gram is improved to about 15 times and 1.7 times. The platform can meet the requirements of small and medium aircraft avionics system for miniaturization, low power consumption and high performance of the computing and processing platform, showing good applicability in the aviation field.

Key words: compactPCI express (CPCIe), multi-core processor, computing and processing platform, symmetrical multi-processing (SMP), signal integrity

CLC Number:

V247.1

YU Dalei, CUI Xining, LI Chengwen, LIU Tingting, ZHOU Yong. Multi-core computing and processing platform based on CPCIe high speed bus in airborne applications[J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2022, 43(5): 325238-325238.

References

[1] 任群. 基于CPCI总线的嵌入式计算机通用接口设计研究[J]. 西安文理学院学报(自然科学版), 2016, 19(1):20-22, 35. REN Q. Research on the design of embedded computer interface based on CPCI bus[J]. Journal of Xi'an University (Natural Science Edition), 2016, 19(1):20-22, 35(in Chinese).
[2] MOIR I, SEABRIDGE A G. Military Avionics Systems[M]. Chichester:John Wiley & Sons Ltd., 2006.
[3] MOIR I, SEABRIDGE A, JUKES M. Civil Avionics Systems[M]. Chichester:John Wiley & Sons Ltd., 2013.
[4] ARINC. Cabin standard enclosures-Modular rack principle (MRP)[S]. Annapolis:Aeronautical Radio, INC., 2012.
[5] AGROU H, GATTI M, SAINRAT P, et al. A design approach for predictable and efficient multi-core processor for avionics[C]//2011 IEEE/AIAA 30th Digital Avionics Systems Conference. Piscataway:IEEE Press, 2011:1-32.
[6] KIM H, RAJKUMAR R. Real-time cache management for multi-core virtualization[C]//Proceedings of the 13th International Conference on Embedded Software. Pittsburgh:ACM, 2016:15.
[7] JEAN X, FAURA D, GATTI M, et al. Ensuring robust partitioning in multicore platforms for IMA systems[C]//2012 IEEE/AIAA 31st Digital Avionics Systems Conference DASC. Piscataway:IEEE Press, 2012:13222073.
[8] LIU J, GUO JH. Energy efficient scheduling of real-time tasks on multi-core processors with voltage islands[J]. Future Generation Computer System, 2016, 56:202-210.
[9] HAN S, JIN H W. Full virtualization based ARINC 653 partitioning[C]//2011 IEEE/AIAA 30th Digital Avionics Systems Conference. Piscataway:IEEE Press, 2011:1-39.
[10] YAO G, PELLIZZONI R, BAK S, et al. Memory-centric scheduling for multicore hard real-time systems[J]. Real-Time Systems, 2012, 48(6):681-715.
[11] FUCHSEN R. How to address certification for multi-core based IMA platforms:current status and potential solutions[C]//29th Digital Avionics Systems Conference. Piscataway:IEEE Press, 2010:5.E.3-1.
[12] AEEC. ARINC specification 653P1-4 avionics application software standard interface set[S]. Bowie:SAE-ITC, 2015.
[13] VxWorks 6533.0 multi-core edition[EB/OL].(2015-05-15)[2021-01-11]. http://www.windriver.com.
[14] 秦涛, 周强, 刘亚斌. CPCIe X1适配卡的关键技术[J]. 计算机工程与设计, 2015, 36(1):263-267. QIN T, ZHOU Q, LIU Y B. Key technique of CPCIe X1 adapter[J]. Computer Engineering and Design, 2015, 36(1):263-267(in Chinese).
[15] 徐健, 张建泉, 张健. 基于PCIE非透明桥的嵌入式异构平台设计[J]. 微电子学与计算机, 2018, 35(1):26-30. XU J, ZHANG J Q, ZHANG J. An application of PCIE non-transparent bridge on A heterogeneous platform[J]. Microelectronics & Computer, 2018, 35(1):26-30(in Chinese).
[16] PCI Special Interest Group.PCI express base specification revision 1.0a[EB/OL].(2014-07-21)[2021-01-11].http://netyi.net/Book.
[17] 周奇, 宣学雷, 贺光辉. 应用于FPGA的PCIe接口设计与验证[J]. 微电子学与计算机, 2019, 36(7):17-21. ZHOU Q, XUAN X L, HE G H. Design and verification of PCIE interface for FPGA[J]. Microelectronics & Computer, 2019, 36(7):17-21(in Chinese).
[18] ROTA L, CASELLE M, CHILINGARYAN S, et al. A PCIe DMA architecture for multi-gigabyte per second data transmission[J]. IEEE Transactions on Nuclear Science, 2015, 62(3):972-976.
[19] 许川佩, 李春丰, 张培源. PCI Express协议事务层设计与仿真[J]. 微电子学与计算机, 2018, 35(9):64-69. XU C P, LI C F, ZHANG P Y. The design and simulation of transaction layer of PCI express protocol[J]. Microelectronics & Computer, 2018, 35(9):64-69(in Chinese).
[20] NACUL A C, REGAZZONI F, LAJOLO M. Hardware scheduling support in SMP architectures[C]//2007 Design, Automation & Test in Europe Conference & Exhibition. Piscataway:IEEE Press, 2007:1-6.
[21] YUAN Q B, BAO Y G, CHEN M Y, et al. A scalability analysis of the symmetric multiprocessing architecture in multi-core system[C]//2009 IEEE International Conference on Networking, Architecture, and Storage. Piscataway:IEEE Press, 2009:231-234.
[22] SAIFULLAH A, AGRAWAL K, LU C Y, et all. Multi-core real-time scheduling for generalized parallel task models[C]//31st IEEE Real-Time Systems Symp. (RTSS). Piscataway:IEEE Press, 2010:217-226.
[23] 耶菲. 过孔桩线对信号完整性的影响以及解决[J]. 航空计算技术, 2018, 48(5):257-260. YE F. Inflence and solution of VIA stub to signal integrity[J]. Aeronautical Computing Technique, 2018, 48(5):257-260(in Chinese).

Multi-core computing and processing platform based on CPCIe high speed bus in airborne applications

RichHTML

PDF (PC)

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics

Comments

[1]	Feng HE, Li ZHANG, Sifan YU, Xuan ZHOU. Schedulability analysis for multi-window partition based on network calculus model [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2023, 44(2): 326581-326581.
[2]	LUO Zexiong, QU Guoyuan, YAN Long, TANG Xueqian. A scheduling table generation method for time-triggered flows based on importance sampling [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2022, 43(3): 325209-325209.
[3]	LI Qiao, LI Jia, XIONG Huagang, YANG Jinhe. Accessing capacity of Deficit Round-Robin (DRR) in avionics very-short range THz interconnections [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2021, 42(6): 624082-624082.
[4]	LU Yao, LI Dongsheng, GAO Yang. Measurement of UAV situation similarity based on sequence trend and set distance [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2019, 40(3): 322453-322453.
[5]	HAO Yukai, CUI Xining, LI Leilei, YANG Qiong. Avionics embedded system benchmark test method [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2016, 37(4): 1327-1335.
[6]	WANG Yu, ZHANG Weiguo, FU Li, HUANG Degang, LI Yong. Dynamic situation assessment method of aerial warfare based on improved evidence network [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2015, 36(12): 3896-3909.
[7]	CHEN Li, WANG Zhongxu, WU Zhaobin, WANG Bo. A Kind of Antiaircraft Weapon-target Optimal Assignment Under Earlier Damage Principle [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2014, 35(9): 2574-2582.
[8]	WANG Guoqing, GU Qingfan, WANG Miao, ZHANG Lihua. Research on the Architecture Technology for New Generation Integrated Avionics System [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2014, 35(6): 1473-1486.
[9]	PU Xiaobo, WANG Yuexing, DENG Hongping, LI Wei. The Classified Pupil Localization Algorithm of Line-of-sight Tracking System [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2012, (6): 1052-1060.
[10]	ZHOU Tianran, XIONG Huagang. Two-level Hierarchical Scheduling for Hybrid Real-time Tasks in Avionic Systems [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2011, 32(6): 1067-1074.
[11]	LU Yi;JIANG Yonghua;ZHAI Longjun;LI Yulong. Study on Ability of Air-to-ship Missile to Acquire the Shape of a Ship Formation [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2011, 32(1): 145-155.
[12]	Lu Yi;Jiang Yonghua. A New Method to Target Selection for Anti-ship Missile [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2010, 31(4): 778-784.
[13]	An Jinxia;Zhu Jihong;Wang Guoqing;Xue Xiaohong. Hierarchical Combination Reliability Modeling Method for Multiple Redundancy Flight Control Computer System [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2010, 31(2): 301-309.
[14]	JING Tong;KANG Ji-chang;TONG Ming-an. ON THE INTERACTIVE TECHNOLOGY IN AIR COMBAT SIMULATION [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2000, 21(3): 270-273.
[15]	Jiang Changsheng;Qiu Li;Sun Longhe;Qi Jianzhong. COMBINATIVE INTELLIGENCE CONTROL OF FCS AND IFFCS OF HELICOPTER WITH WEAPON [J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 1997, 18(4): 401-406.