基于CPCIe高速总线的机载多核计算处理平台

doi:10.7527/S1000-6893.2021.25238

Abstract

Abstract: As the avionics system of small and medium aircraft has strict restrictions on the volume, power consumption and weight of the computing and processing platform, it is necessary to design the computing and processing platform with high performance, miniaturization and low power consumption. An airborne computing and processing platform architecture based on the CPCIe (CompactPCI Express) high-speed bus and multi-core processor is studied. The adaptability of multi-core processing and high-speed signal integrity to the avionics system is realized. A distributed airborne multi-core computing platform is designed and implemented based on the CPCIe high-speed bus. Signal integrity of the CPCIe bus is simulated and tested. The computing processing platform is implemented and verified in the avionics system. Compared with the traditional joint architecture and integrated modular architecture, the performance per watt of the platform proposed is improved to about 7 times and 5 times, the performance per cubic centimeter is improved to about 24 times and 2 times, and the performance per gram is improved to about 15 times and 1.7 times. The platform can meet the requirements of small and medium aircraft avionics system for miniaturization, low power consumption and high performance of the computing and processing platform, showing good applicability in the aviation field.

Key words: compactPCI express (CPCIe), multi-core processor, computing and processing platform, symmetrical multi-processing (SMP), signal integrity

CLC Number:

V247.1

YU Dalei, CUI Xining, LI Chengwen, LIU Tingting, ZHOU Yong. Multi-core computing and processing platform based on CPCIe high speed bus in airborne applications[J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2022, 43(5): 325238-325238.

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Multi-core computing and processing platform based on CPCIe high speed bus in airborne applications

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