[1] |
FEYNMAN J, GABRIEL B. High-energy charged particles in space at one astronomical unit[J]. IEEE Transactions on Nuclear Science, 1996, 43(2):344-352.
|
[2] |
NORMAND E. Single event upset at ground level[J]. IEEE Transactions on Nuclear Science, 1996, 43(6):2742-2750.
|
[3] |
CARMICHAEL C, CAFFREY M, SALAZAR A, et al. Correcting single-event upsets through Virtex partial configuration[EB/OL]. (2000-06-01)[2019-05-29]. http://ebook.pldworld.com/_semiconduc-tors/Xilinx/DataSource%20CD-ROM/Rev.5%20(Q4-2001)/appnotes/xapp216.pdf.
|
[4] |
HAMMING R W. Error detecting and error correcting codes[J]. The Bell System Technical Journal, 1950, 29(2):147-160.
|
[5] |
CHEN C L, HSIAO M Y. Error-correcting codes for semiconductor memory applications:A state-of-the-art Review[J]. IBM Journal of Research and Development, 1984, 28(2):124-134.
|
[6] |
曹晖, 郑渊, 刘伟鑫, 等. 宇航用SRAM存储器单粒子效应试验研究[J]. 上海航天, 2013, 30(3):60-64. CAO H, ZHENG Y, LIU W X, et al. Single-event effect test of SRAM memory for aerospace[J]. Shanghai Aerospace, 2013, 30(3):60-64(in Chinese).
|
[7] |
MOON T K. Error correction coding. Mathematical methods and algorithms[M], Hoboken, NJ:Jhon Wiley and Son, 2005:2001-2006.
|
[8] |
ROBERT G. Low-density parity-check codes[J]. IRE Transactions on Information Theory, 1962, 8(1):21-28.
|
[9] |
IROM F, NGUYEN D. Single event effect characterization of high density commercial NAND and NOR nonvolatile flash memories[J]. IEEE Transactions on Nuclear Science, 2007, 54(6):2547-2553.
|
[10] |
HEIDEL D F, MARSHALL P W, PELLISH J A, et al. Single-event upsets and multiple-bit upsets on a 45 nm SOI SRAM[J]. IEEE Transactions on Nuclear Science, 2009, 56(6):3499-3504.
|
[11] |
SINGH A K. Error detection and correction by hamming code[C]//International Conference on Global Trends in Signal Processing, Information Computing and Communication. Piscataway, NJ:IEEE Press, 2016.
|
[12] |
GOPPA V D. A new class of linear correcting codes[J]. Probl Peredachi Information, 1970, 6(3):24-30.
|
[13] |
KOOPMAN P, CHAKRAVARTY T. Cyclic redundancy code (CRC) polynomial selection for embedded networks[C]//International Conference on Dependable Systems and Networks. Piscataway, NJ:IEEE Press, 2004.
|
[14] |
QUINN H, GRAHAM H, KRONE J, et al. Multi-bit upsets in the Virtex devices[R]. Washington, D.C.:NASA, 2007.
|
[15] |
PLANK J S. A tutorial on Reed-Solomon coding for fault-tolerance in RAID-like systems[J]. Software:Practice and Experience, 1997, 27(9):995-1012.
|
[16] |
ZHOU, Y, HE F Z, HOU N, et al. Parallel ant colony optimization on multi-core SIMD CPUs[J]. Future Generation Computer Systems, 2018, 79(2):473-487.
|
[17] |
PLANK J S, SCHUMAN C D, ROBISON B D, et al. Heuristics for optimizing matrix-based erasure codes for fault-tolerant storage systems[C]//IEEE/IFIP International Conference on Dependable Systems and Networks. Piscataway, NJ:IEEE Press, 2012.
|
[18] |
ZHOU J R, ROSS K A. Implementing database operations using SIMD instructions[C]//Proceedings of the International Conference on Management of Data. New York:ACM, 2002.
|
[19] |
MARTON K, RALUCA B, SUCIU A. Counting bits in parallel[C]//Networking in Education and Research (RoEduNet). Piscataway, NJ:IEEE Press, 2017.
|
[20] |
刘凯哲. 单粒子效应在轨翻转率预计研究[D]. 哈尔滨:黑龙江大学, 2014:39-48. LIU K Z. Research on single-particle effect in-orbit flip rate prediction[D]. Harbin:Heilongjiang University, 2014:39-48(in Chinese).
|