Abstract: To address the issues of low detection accuracy, high computational cost, and resource scheduling imbalance in the edge deployment of infrared small target detection, a hardware-software co-design acceleration method for reconfigurable edge deployment is proposed. At the algorithmic level, a lightweight network, SCAD-SSD, is constructed: the High-resolution Adaptation and Anchor Specialization (HAAS) strategy is utilized to reconstruct sampling density and alleviate weak signal annihilation; the Sparse Contextual awareness Block (SCB) is designed to mine environmental cues for signal enhancement; and the Adaptive Discriminative Rejection (ADR) module is integrated to build a feature filtering mechanism for background suppression. At the hardware level, a SoC-based parallel acceleration architecture is developed: a Dimensional Parallel-Access Unit (DPAU) is designed to optimize on-chip data reuse; a Universal Parameterized Reconfigurable Engine (UPRE) with a global task scheduling mechanism is proposed to effectively mask pipeline stalls through dynamic resource reorganization and dual-engine load balancing. Experimental results show that SCAD-SSD achieves 97.74% AP50 and 96.49% recall on the IRSTD-UAV benchmark, with a inference speed of 104.0 FPS on the GPU, and shows good cross-scenario generalization potential. With a minimal overhead of 3.69 M parameters and 6.64 GFLOPs, the hardware accelerator achieves a throughput of 71.05 GOPS and an actual running frame rate of 10.7 FPS on the Zynq-7020 platform, yielding an energy efficiency of 21.02 GOPS/W. The proposed method improves detection sensitivity while meeting the requirements of real-time detection and reliable defense at the edge.

Key words: UAV detection, infrared small target, FPGA accelerator, hardware-software co-design, sparse contextual awareness, reconfigurable computing