The advanced distributed integrated avionics system needs to achieve information integration across computing architectures. Integrated interconnection among micro-smart devices is thus required. By constructing an off-chip integrated interconnection structure with the open interface, a corresponding time-triggered message scheduling method is proposed. First, the off-chip interconnection model and the Time-Triggered (TT) communication model are established, and the load balancing path selection method is given. Then, the feasible value of the waiting time is calculated according to the flow's transmission offset of chips in the transmission path. The genetic algorithm is used to adjust the phase of scheduling tables of chips' send ports, whereby the flow's transmission offset can be updated and the maximum waiting time of the worst case can be shortened. The time-triggered scheduling table with global optimization significance can be obtained. Compared with the methods of generating TT scheduling tables using the SMT formalizer, such as Yices, this method does not work for a long time without stopping and can not cause undefined problems. The case study shows that the scheduler scale of this method increases by at least 30% for both symmetric and asymmetric structures. In addition, the ratio of the waiting time to the time period is taken as the normalized transmission delay metric. The case study also shows that the propagation delay value deduced by this method reduces to less than 2% of the one deduced by existing task-based scheduling methods.
KONG Yunwen
,
LI Qiao
,
XIONG Huagang
,
CHENG Zijing
. Time-triggered communication scheduling method for off-chip integrated interconnection[J]. ACTA AERONAUTICAET ASTRONAUTICA SINICA, 2018
, 39(2)
: 321590
-321590
.
DOI: 10.7527/S1000-6893.2017.21590
[1] 熊华钢, 王中华. 先进航空电子综合技术[M]. 北京:国防工业出版社, 2009:2-13. XIONG H G, WANG Z H. Advanced avionics integration techniques[M]. Beijing:National Defense Industry Press, 2009:2-13(in Chinese)[2] 王国庆, 谷青范, 王淼, 等. 新一代综合化航空电子系统构架技术研究[J]. 航空学报, 2014, 35(6):1473-1486. WANG G Q, GU Q F, WANG M, et al. Research on the architecture technology for new generation integrated avionics system[J]. Acta Aeronautica et Aastronautica Sinica, 2014, 35(6):1473-1486(in Chinese).[3] WOLFIG R, JAKOVLJEVIC M. Distributed IMA and DO-297:Architectural, communication and certification attributes[C]//Proceedings Digital Avionics Systems Conference. Piscataway, NJ:IEEE Press, 2008:1.E.4-1-1.E.4-10.[4] 蒲小勃. 现代航空电子系统与综合[M]. 北京:航空工业出版社, 2013:70-86. PU X B. Modern avionics system and integration[M]. Beijing:Aviation Industry Press, 2013:70-86(in Chinese).[5] DARPA M T O. Another big shrink:Tiling chiplets into next-generation microsystems[EB/OL]. (2016-07-19)[2017-07-05].http://www.darpa.mil/news-events/2016-07-19.[6] E2V. E2V and Adeneo partner to the world's smallest, multicore computer for aerospace applications[EB/OL]. (2016-07-18)[2017-07-05].https://www.e2v.com/news/e2v-and-adeneo-partner-to--the-worlds-smallest-multicore-computer-for-aerospace-applications/.[7] 林闯, 贾子骁, 孟坤. 自适应的未来网络体系架构[J]. 计算机学报, 2012, 35(6):1077-1093. LIN C, JIA Z X, MENG K. Research on adaptive future internet architecture[J]. Chinese Journal of Computer,2012, 35(6):1077-1093(in Chinese).[8] HIERGEIST S, HOLZAPFEL F. Fault-tolerant FCC Architecture for future UAV systems based on COTS SoC[C]//Proceedings Architecture of Computing Systems. Berlin:Springer International Publishing, 2016:1-5.[9] SCHECKEL T. Serial RapidlO:Benefiting system interconnects[C]//Proceedings SOC Conference. Piscataway,NJ:IEEE Press, 2005:317-318.[10] LEENS F. An introduction to I 2 C and SPI protocols[J]. IEEE Instrumentation & Measurement Magazine, 2009, 12(1):8-13.[11] DURRIEU G, FOHLER G, GALA G, et al. DREAMS about reconfiguration and adaptation in avionics[C]//Proceedings Embedded Real Time Software and Systems. Toulouse:European Congress Press. 2016:48-57.[12] OLIVER R S, CRACIUNAS S S. Hierarchical scheduling over off-and on-chip deterministic networks[J]. Acm Sigbed Review, 2016, 13(4):14-19.[13] OBERMAISSER R, EL SALLOUM C, HUBER B, et al. The time-triggered system-on-a-chip architecture[C]//Proceedings IEEE International Symposium on Industrial Electronics. Piscataway,NJ:IEEE Press, 2008:1941-1947.[14] WASICEK A, EI-SALLOUM C, KOPETZ H. A system-on-a-chip platform for mixed-criticality applications[C]//Proceedings IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing. Piscataway, NJ:IEEE Press, 2010:210-216.[15] SCHOEBERL M. A time-triggered network-on-chip[C]//Proceedings International Conference on Field Programmable Logic and Applications. Piscataway,NJ:IEEE Press, 2007:377-382.[16] STEINER W. An evaluation of SMT-based schedule synthesis for time-triggered multi-hop networks[C]//Pro-ceedings Real-Time Systems Symposium. Piscataway, NJ:IEEE Press, 2011:375-384.[17] POZO PÉREZ F M, RODRIGUEZ NAVAS G, HANSSON H, et al. Schedule synthesis for next generation time-triggered networks[C]//IEEE 20th Conference on Emerging Technologies & Factory Automation (ETFA).Piscataway, NJ:IEEE Press, 2015:1-8.[18] CRACIUNAS S S, OLIVER R S. SMT-based task-and network-level static schedule generation for time-triggered networked systems[C]//Proceedings International Conference on Real-Time Networks and Systems. Versailles:RTNS Press, 2014:45-54.[19] HU M, LUO J, WANG Y, et al. Scheduling periodic task graphs for safety-critical time-triggered avionic systems[J]. IEEE Transactions on Aerospace & Electronic Systems, 2015, 51(3):2294-2304.[20] CHEN J, DU C, XIE F, et al. Schedulability analysis of non-preemptive strictly periodic tasks in multi-core real-time systems[J]. Real-Time Systems, 2016, 52(3):239-271.[21] 陈进朝, 杜承烈. 单处理器平台下的严格周期任务可调度性判定[J]. 计算机工程, 2016, 42(5):288-291. CHEN J C, DU C L. Schedulability test for strictly periodic tasks in uniprocessor systems[J]. Computer Engineering, 2016, 42(5):288-291(in Chinese).[22] TTE-COM. TTE-COM A653 for VxWorks 6532.4[EB/OL]. (2016-10-25)[2017-07-05]. Vienna, Austria:TTTech Computertechnik AG, 2016.https://www.tttech.com/products/aerospace/development-test-vv/middleware/tte-com-a653-for-vxworks-653/.[23] SAE. Time-triggered Ethernet:AS6802[S]. Warrendale, PA:SAE International, 2011.[24] DING S, YIN X, XU H, et al. A hybrid GA-based scheduling method for static segment in FlexRay systems[C]//Proceedings Control and Decision Conference. Piscataway, NJ:IEEE Press, 2010:1548-1552.[25] 代真, 何锋, 张宇静, 等.AFDX虚拟链路路径实时寻优算法[J]. 航空学报, 2015, 36(6):1924-1932. DAI Z, HE F, ZHANG Y J, et al. Real-time path optimization algorithm of AFDX virtual link[J]. Acta Aeronautica et Astronautica Sinica, 2015, 36(6):1924-1932(in Chinese).[26] DUTERTRE B. Yices 2.2[C]//Proceedings International Conference on Computer Aided Verification. Berlin:Springer International Publishing, 2014:737-744.
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