由于中小型飞机航空电子系统对计算处理平台体积、功耗和重量方面的严格限制，有必要对计算处理平台进行高性能、小型化、低功耗的针对性设计。研究了一种基于CPCIe （CompactPCI Express）高速总线和多核处理器的机载计算处理平台架构，攻克了多核处理和CPCIe高速信号完整性在航空电子系统中的适应性问题，设计并实现了一款基于CPCIe高速总线的分布式机载多核计算处理平台，对CPCIe总线信号完整性进行了仿真和测试，最后在航空电子系统中对计算处理平台进行实施验证。相比于传统的联合式架构和综合模块化架构，计算处理平台的性能功耗比分别提升约7倍、5倍，性能体积比分别提升约24倍、2倍，性能重量比分别提升约15倍、1.7倍，可以满足中小型飞机航空电子系统对计算处理平台小型化、低功耗和高性能的需求，具有较好的工程应用参考价值，在航空领域具有广泛的应用前景。
As the avionics system of small and medium aircraft has strict restrictions on the volume, power consumption and weight of the computing and processing platform, it is necessary to design the computing and processing platform with high performance, miniaturization and low power consumption. An airborne computing and processing platform architecture based on the CPCIe (CompactPCI Express) high-speed bus and multi-core processor is studied. The adaptability of multi-core processing and high-speed signal integrity to the avionics system is realized. A distributed airborne multi-core computing platform is designed and implemented based on the CPCIe high-speed bus. Signal integrity of the CPCIe bus is simulated and tested. The computing processing platform is implemented and verified in the avionics system. Compared with the traditional joint architecture and integrated modular architecture, the performance per watt of the platform proposed is improved to about 7 times and 5 times, the performance per cubic centimeter is improved to about 24 times and 2 times, and the performance per gram is improved to about 15 times and 1.7 times. The platform can meet the requirements of small and medium aircraft avionics system for miniaturization, low power consumption and high performance of the computing and processing platform, showing good applicability in the aviation field.
[1] 任群. 基于CPCI总线的嵌入式计算机通用接口设计研究[J]. 西安文理学院学报(自然科学版), 2016, 19(1):20-22, 35. REN Q. Research on the design of embedded computer interface based on CPCI bus[J]. Journal of Xi'an University (Natural Science Edition), 2016, 19(1):20-22, 35(in Chinese).
[2] MOIR I, SEABRIDGE A G. Military Avionics Systems[M]. Chichester:John Wiley & Sons Ltd., 2006.
[3] MOIR I, SEABRIDGE A, JUKES M. Civil Avionics Systems[M]. Chichester:John Wiley & Sons Ltd., 2013.
[4] ARINC. Cabin standard enclosures-Modular rack principle (MRP)[S]. Annapolis:Aeronautical Radio, INC., 2012.
[5] AGROU H, GATTI M, SAINRAT P, et al. A design approach for predictable and efficient multi-core processor for avionics[C]//2011 IEEE/AIAA 30th Digital Avionics Systems Conference. Piscataway:IEEE Press, 2011:1-32.
[6] KIM H, RAJKUMAR R. Real-time cache management for multi-core virtualization[C]//Proceedings of the 13th International Conference on Embedded Software. Pittsburgh:ACM, 2016:15.
[7] JEAN X, FAURA D, GATTI M, et al. Ensuring robust partitioning in multicore platforms for IMA systems[C]//2012 IEEE/AIAA 31st Digital Avionics Systems Conference DASC. Piscataway:IEEE Press, 2012:13222073.
[8] LIU J, GUO JH. Energy efficient scheduling of real-time tasks on multi-core processors with voltage islands[J]. Future Generation Computer System, 2016, 56:202-210.
[9] HAN S, JIN H W. Full virtualization based ARINC 653 partitioning[C]//2011 IEEE/AIAA 30th Digital Avionics Systems Conference. Piscataway:IEEE Press, 2011:1-39.
[10] YAO G, PELLIZZONI R, BAK S, et al. Memory-centric scheduling for multicore hard real-time systems[J]. Real-Time Systems, 2012, 48(6):681-715.
[11] FUCHSEN R. How to address certification for multi-core based IMA platforms:current status and potential solutions[C]//29th Digital Avionics Systems Conference. Piscataway:IEEE Press, 2010:5.E.3-1.
[12] AEEC. ARINC specification 653P1-4 avionics application software standard interface set[S]. Bowie:SAE-ITC, 2015.
[13] VxWorks 6533.0 multi-core edition[EB/OL].(2015-05-15)[2021-01-11]. http://www.windriver.com.
[14] 秦涛, 周强, 刘亚斌. CPCIe X1适配卡的关键技术[J]. 计算机工程与设计, 2015, 36(1):263-267. QIN T, ZHOU Q, LIU Y B. Key technique of CPCIe X1 adapter[J]. Computer Engineering and Design, 2015, 36(1):263-267(in Chinese).
[15] 徐健, 张建泉, 张健. 基于PCIE非透明桥的嵌入式异构平台设计[J]. 微电子学与计算机, 2018, 35(1):26-30. XU J, ZHANG J Q, ZHANG J. An application of PCIE non-transparent bridge on A heterogeneous platform[J]. Microelectronics & Computer, 2018, 35(1):26-30(in Chinese).
[16] PCI Special Interest Group.PCI express base specification revision 1.0a[EB/OL].(2014-07-21)[2021-01-11].http://netyi.net/Book.
[17] 周奇, 宣学雷, 贺光辉. 应用于FPGA的PCIe接口设计与验证[J]. 微电子学与计算机, 2019, 36(7):17-21. ZHOU Q, XUAN X L, HE G H. Design and verification of PCIE interface for FPGA[J]. Microelectronics & Computer, 2019, 36(7):17-21(in Chinese).
[18] ROTA L, CASELLE M, CHILINGARYAN S, et al. A PCIe DMA architecture for multi-gigabyte per second data transmission[J]. IEEE Transactions on Nuclear Science, 2015, 62(3):972-976.
[19] 许川佩, 李春丰, 张培源. PCI Express协议事务层设计与仿真[J]. 微电子学与计算机, 2018, 35(9):64-69. XU C P, LI C F, ZHANG P Y. The design and simulation of transaction layer of PCI express protocol[J]. Microelectronics & Computer, 2018, 35(9):64-69(in Chinese).
[20] NACUL A C, REGAZZONI F, LAJOLO M. Hardware scheduling support in SMP architectures[C]//2007 Design, Automation & Test in Europe Conference & Exhibition. Piscataway:IEEE Press, 2007:1-6.
[21] YUAN Q B, BAO Y G, CHEN M Y, et al. A scalability analysis of the symmetric multiprocessing architecture in multi-core system[C]//2009 IEEE International Conference on Networking, Architecture, and Storage. Piscataway:IEEE Press, 2009:231-234.
[22] SAIFULLAH A, AGRAWAL K, LU C Y, et all. Multi-core real-time scheduling for generalized parallel task models[C]//31st IEEE Real-Time Systems Symp. (RTSS). Piscataway:IEEE Press, 2010:217-226.
[23] 耶菲. 过孔桩线对信号完整性的影响以及解决[J]. 航空计算技术, 2018, 48(5):257-260. YE F. Inflence and solution of VIA stub to signal integrity[J]. Aeronautical Computing Technique, 2018, 48(5):257-260(in Chinese).
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